Those who follow the single makefile approach outlined by Peter Miller in his excellent paper Recursive Make Considered Harmful may be interested in the -MT option to the GCC preprocessor, introduced after Peter wrote the paper. This switch allows the target name to be explicitly defined, multiple times if required, instead of being derived from the source file name. An sample command to be inserted into the makefile (instead of using depend.sh in Peter's example) is
$(CC) $(CFLAGS) -MM -MG -MT $(OBJ_DIR)/$(*).o -MT $(DEP_DIR)/$(*).d -MF $@ $<
Notice that I keep my dynamic dependency files in a separate directory to the source code.

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